The present invention relates generally to memory devices and in particular the present invention relates to power validation of circuits of memory devices.
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM is read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU""s bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM""s can be accessed quickly, but are volatile.
Many memory devices include system circuits that need to be initialized before the memory can be powered up for reliable operation. A problem may arise when the memory device has multiple power supply connections. Some signals that work off the power supplied to one supply connection may need to interact with other signals that work off the power supplied to another supply connection. If one supply is fully powered up and the other is not fully powered up, the reliability of operations becomes questionable.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art to verify power levels at the power supply connections before the system circuits are initialized.
The above-mentioned problems with integrated circuit dice having multiple power supply connections and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, each power supply connection is coupled to an associated low power sense circuit. Each low power sense circuit provides an output signal when a voltage is detected on its associated power supply connection that is above a predetermined threshold voltage. A logic circuit is coupled to the outputs of each low power sense circuit. When the output of each power sense circuit has been detected by the logic circuit, the logic circuit sends a signal to a control circuit. The control circuit then allows the memory to be initialized.
In another embodiment, a memory system comprises, an external processor, non-volatile memory having a plurality of power supply connections, a power validation circuit, an array of memory cells and a control unit. The non-volatile memory is coupled to the external processor. The power validation circuit is coupled to the plurality of power supply connections. The power validation circuit provides an output signal to indicate a status of each of the plurality of power supply connections relative to an associated threshold voltage. The control circuit controls memory operation functions of the array of memory cells in response to the output signal of the validation circuit.
A method of operating a memory having a plurality of power supply connections is described. The method comprises monitoring power supply voltages on power supply connections, comparing the power supply voltages on the power supply connections with an associated threshold voltage and ignoring externally provided commands while the power supply voltages are below a predetermined threshold voltage.
Another method of operating a memory having a plurality of power supply connections is described. The method comprises monitoring power supply voltages on power supply connections, comparing the power supply voltages on the power supply connections with an associated threshold voltage and prohibiting initialization of memory while power supply voltages are below predetermined threshold voltages.